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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 2,673 public repositories matching this topic...

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power

Updated Mar 24, 2021
Verilog

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

fpga core riscv verilog risc-v

Updated Jul 16, 2025
Verilog

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Aug 14, 2025
Verilog

pConst / basic_verilog

Must-have verilog systemverilog modules

Updated Aug 2, 2025
Verilog

analogdevicesinc / hdl

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Aug 14, 2025
Verilog

serv

olofk / serv

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Jun 5, 2025
Verilog

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203

Updated Aug 6, 2025
Verilog

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

ZipCPU / zipcpu

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Aug 9, 2025
Verilog

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

circuitvalley / USB_C_Industrial_Camera_FPGA_USB3

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

fpga usb camera verilog csi uvc usb3 mipi mipi-csi-receiver

Updated Oct 22, 2023
Verilog

splinedrive / kianRiscV

RISC-V Linux SoC, marchID: 0x2b

linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc bare-metal rv32ima chipdesign tinytapeout sv32

Updated Aug 14, 2025
Verilog

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

lvyufeng / step_into_mips

一步一步写MIPS CPU

verilog mips-cpu nscscc

Updated Aug 4, 2021
Verilog

Obijuan / open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

linux fpga verilog icestorm lattice fpgawars openfpga

Updated Apr 15, 2020
Verilog

WangXuan95 / FPGA-USB-Device

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

Updated Dec 6, 2024
Verilog

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Aug 5, 2025
Verilog

xiaop1 / Verilog-Practice

HDLBits website practices & solutions

practice verilog hdlbits

Updated Dec 27, 2023
Verilog

WangXuan95 / FPGA-FOC

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

fpga motor verilog systemverilog field-oriented-control bldc pmsm foc svpwm

Updated Sep 15, 2023
Verilog

rejunity / z80-open-silicon

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

cpu foss z80 verilog chip retrocomputing tapeout tinytapeout

Updated Jun 11, 2025
Verilog

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