32-bit Superscalar RISC-V CPU
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
Advanced Architecture Labs with CVA6
Super scalar Processor design
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
Kite: Architecture Simulator for RISC-V Instruction Set
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
Computer Architecture UIUC SP 2018
Computer architecture related projects
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
VHDL code of three branch predictors
System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.
2 bit saturated branch predictor with BHR (Branch History Register)
Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.
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