Digital logic design tool and simulator
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Updated
Sep 3, 2024 - Java
Digital logic design tool and simulator
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Haskell to VHDL/Verilog/SystemVerilog compiler
Hardware Description Languages
VUnit is a unit testing framework for VHDL/SystemVerilog
An abstraction library for interfacing EDA tools
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
A List of Free and Open Source Hardware Verification Tools and Frameworks
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