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@SpinalHDL

SpinalHDL

A high level hardware description language

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  1. SpinalHDL Public

    Scala based HDL

    Scala 1.8k 345

  2. VexRiscv Public

    A FPGA friendly 32 bit RISC-V CPU implementation

    Assembly 2.7k 443

  3. SpinalTemplateSbt Public template

    A basic SpinalHDL project

    Scala 85 69

  4. SpinalWorkshop Public

    Labs to learn SpinalHDL

    Scala 146 42

  5. SpinalDoc-RTD Public

    The sources of the online SpinalHDL doc

    Python 26 62

  6. Spinal-bootcamp Public

    Forked from jijingg/Spinal-bootcamp

    SpinalHDL-tutorial based on Jupyter Notebook

    Jupyter Notebook 44 7

Repositories

Showing 10 of 42 repositories
  • SpinalHDL Public

    Scala based HDL

    Scala 1,772 345 138 (6 issues need help) 29 Updated Apr 23, 2025
  • VexRiscv Public

    A FPGA friendly 32 bit RISC-V CPU implementation

    Assembly 2,736 MIT 443 108 5 Updated Apr 23, 2025
  • SpinalDoc-RTD Public

    The sources of the online SpinalHDL doc

    Python 26 CC0-1.0 62 22 (4 issues need help) 6 Updated Apr 20, 2025
  • VexiiRiscv-RTD Public
    Python 1 CC0-1.0 3 0 1 Updated Apr 20, 2025
  • rvls Public

    RISCV lock-step checker based on Spike

    C++ 10 3 0 0 Updated Apr 17, 2025
  • VexiiRiscv Public

    Like VexRiscv, but, Harder, Better, Faster, Stronger

    Scala 150 MIT 17 5 0 Updated Apr 15, 2025
  • SpinalTemplateSbt Public template

    A basic SpinalHDL project

    Scala 85 69 5 5 Updated Apr 6, 2025
  • NaxSoftware Public
    C 9 5 0 0 Updated Mar 20, 2025
  • SpinalSchemaGen Public
    Scala 5 MIT 1 0 0 Updated Mar 17, 2025
  • SaxonSoc Public

    SoC based on VexRiscv and ICE40 UP5K

    Scala 157 MIT 41 15 0 Updated Mar 16, 2025
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