vhdl
Here are 105 public repositories matching this topic...
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
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Jun 20, 2024 - Verilog
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
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Aug 27, 2023 - Verilog
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
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Aug 12, 2017 - Verilog
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
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Dec 3, 2023 - Verilog
Hardware Formal Verification
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Aug 10, 2020 - Verilog
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
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Oct 25, 2023 - Verilog
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
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Aug 13, 2023 - Verilog
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
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Sep 10, 2023 - Verilog
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
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Apr 12, 2020 - Verilog
Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-
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Mar 22, 2021 - Verilog
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
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Jun 3, 2024 - Verilog
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
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Mar 22, 2024 - Verilog
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
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Oct 30, 2017 - Verilog
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
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Mar 30, 2022 - Verilog
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