#

migen

Here are 21 public repositories matching this topic...

rprinz08 / hBPF

hBPF = eBPF in hardware

fpga python3 ebpf litex migen

Updated Jan 27, 2023
Python

fomu-workshop

im-tomu / fomu-workshop

Support files for participating in a Fomu workshop

fpga vhdl chisel riscv verilog hdl litex migen fomu fomu-workshop

Updated Mar 17, 2024
Verilog

quartiq / bscan_spi_bitstreams

FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.

fpga migen

Updated Mar 16, 2023
Python

peteut / migen-axi

AXI support for Migen/MiSoC

hdl misoc migen zynq-7000

Updated Jul 21, 2024
Python

fallen / SucreLA

Open source Logic Analyzer based on LiteX SoC

fpga logic analyzer risc-v litex migen ecp5 hydrausb3

Updated Dec 21, 2024
C

sergachev / litex-template

Template project for LiteX-based SoCs

system-on-chip litex migen

Updated Jul 11, 2024
Python

apertus-open-source-cinema / axiom-micro-gateware

gateware for the main fpga, including a hispi decoder and image processing

fpga image-processing image-sensor axiom migen apertus hispi

Updated Sep 27, 2018
Verilog

rohitk-singh / usb-device

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

usb python3 usb-devices migen ip-core

Updated Oct 24, 2017
Verilog

JC-LL / ruby_rtl

Describing RTL circuit in Ruby

dsl vhdl hdl digital-circuits migen

Updated Mar 17, 2022
Ruby

zignig / tinybx_stuff

Scripts and gateware for the TinyFPGA bx

migen tinyfpga nmigen

Updated Mar 18, 2020
AGS Script

quartiq / fastino

Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)

fpga dsp artiq migen sinara-hw

Updated Mar 2, 2023
Python

timvideos / qemu-litex

fpga qemu fpga-soc-linux or1k fpga-soc openrisc litex misoc migen liteeth

Updated Sep 13, 2018
C

freddy- / migen-playground

fpga litex migen

Updated Apr 11, 2020
Python

quartiq / urukul

CPLD gateware for the Sinara Urukul module

fpga cpld artiq migen sinara-hw

Updated Nov 18, 2021
Python

Bucknalla / warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip verilog migen open-cores

Updated Mar 17, 2020
Tcl

MaxenceCaronLasne / unitbench

A unit-test framework for testing Migen modules directely on hardware.

fpga hardware test-framework migen

Updated Jan 23, 2020
Python

quartiq / mirny

CPLD gateware for the Sinara Mirny module.

fpga cpld artiq migen sinara-hw

Updated Aug 20, 2024
Python

Sajjadranjbar / migen_examples

Migen framework examples

verilog hdl migen

Updated Oct 21, 2018
Python

chmousset / hmmc

Hardware Motion and Motor Control Library

fpga cnc-controller bldc pmsm litex motion-control migen foc motor-control servomotor-control

Updated Jul 22, 2023
Python

Sparsh2208 / Computer-Organisation-Architecture-Projects

A simple C++ project configured for use with Visual Studio Code, including IntelliSense support, custom file associations, and a GitHub Actions workflow for continuous integration. COA LiTEX

cpp risc-v coa migen

Updated Aug 16, 2024
C++

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