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You must be logged in to vote 🙏 Vivado synthesis and loop limit for IMEM as ROM
enhancementNew feature or request HWHardware-related -
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You must be logged in to vote 🙏 Problems with missing custom files used for CFS in Vivado IP block
customizationTailoring the core to your needs -
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You must be logged in to vote 🙌 NEORV32 as Vivado IP
HWHardware-related howtoHands-on expertise / tutorial / user guide -
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You must be logged in to vote 🙏 How to create tri-state interface in block design?
HWHardware-related troubleshootingSomething is not working as expected -
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You must be logged in to vote 🙏 How to simulate a (minimal example) block design containing the packaged IP
bugSomething isn't working as expected HWHardware-related -
You must be logged in to vote 🙏 Replicating existing modules - further extend UART ports
HWHardware-related SWSoftware-related howtoHands-on expertise / tutorial / user guide customizationTailoring the core to your needs -
You must be logged in to vote 💬 Multi-Core Architecture
enhancementNew feature or request help wantedExtra attention is needed -
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You must be logged in to vote 🙏 Where is the bus error triggered for accessing "the void"
HWHardware-related