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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 103 public repositories matching this topic...

HWAC-DL / hwac_object_tracker

FPGA accelerated TinyYOLO v2 object detection neural network

fpga detection verilog xilinx vivado pynq tinyyolo

Updated Jul 31, 2018
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jtgebert / fpganes_release

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

python java fpga nes verilog de1-soc system-verilog

Updated May 12, 2017
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nekosilverfox / ZYNQ

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

sdk fpga zynq verilog xilinx vivado zynq-7010 zynq-7000 soc-fpga zynq-7020 soc-design

Updated Dec 31, 2021
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Triple-Z / COExperiment_Repo

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

cpu mips verilog computer-organization

Updated Jul 4, 2017
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kittennbfive / 5A-75B-tools

a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys

fpga verilog yosys ecp5 colorlight nextpnr 5a-75b chubby75 nextpnr-ecp5

Updated Oct 20, 2023
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asonnino / fourier-transmitter

A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.

fpga verilog transmitter fourier-transform qam-modulation virtex7

Updated Jan 27, 2021
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ZipCPU / website

The ZipCPU blog

blog learning tutorial fpga verilog verilator zipcpu zipcpu-blog

Updated Jun 20, 2025
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SivannaKing / SEU-ASIC-IOT-ECGAI

Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators

deep-learning accelerator cnn verilog

Updated Jun 5, 2023
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FliPGA01

pescetti-studio / FliPGA01

FPGA (Verilog) implementation of the Flip01 8-bit processor.

cpu fpga verilog 8bit 8-bit verilog-project 8-bit-cpu 8-bit-computer flip01

Updated Dec 30, 2024
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SravanChittupalli / 8-bit-ALU-in-verilog

8-bit ALU in Verilog.

verilog alu hdl testbench

Updated Nov 16, 2020
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ChamanAgrawal / CS220

This repository contains lab assignments done in the course CS220: Computer Organization at IIT Kanpur

verilog xilinx-fpga computer-organization

Updated Aug 8, 2019
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djzenma / 2-FPGAs-UART-Protocol

Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.

fpga verilog hardware-designs uart-protocol verilog-project

Updated Aug 31, 2018
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asyncze / code

My technical notes as bite-sized executable programs

python rust pascal machine-learning scala algorithms cpp assembly rust-lang verilog problem-solving system-programming euler-project c-lang

Updated Jun 9, 2024
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Muslim-314 / AES_over_UART

The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.

communication-protocol communication python3 verilog uart aes-encryption secure-communication aes-decryption cyclic-redundancy-check

Updated Jun 7, 2024
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abdcelik / GtuEdu

Gebze Technical University

python c java cpp common-lisp prolog verilog

Updated Jul 27, 2023
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MalakSadek / StaticTimingAnalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

python c html json graph-algorithms scl verilog logic-gates verilog-hdl logic-circuit static-timing-analysis

Updated Mar 25, 2021
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MengmSun / flappybrick

Nexys4FPGA game, verilog, imitate FlappyBird

verilog verilog-project

Updated Nov 30, 2020
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Ncerzzk / FPGA-PWM

A fpga based pwm module.(support I2C and SPI protocol)

fpga verilog spinalhdl

Updated Oct 11, 2023
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NeilNie / LC-3

Verilog Implementation of the LC-3 Processor. DA CS 603

verilog quartus lc-3 quartus2

Updated Mar 6, 2019
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izumizawa / mc851

Projeto com objetivo de desenvolver um sistema computacional contendo, ao menos, um processador e seus componentes periféricos.

fpga verilog risc-v

Updated Dec 2, 2023
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Website: github.com/topics/verilog
Wikipedia: Wikipedia