OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Project F brings FPGAs to life with exciting open-source designs you can build on.

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Test suite designed to check compliance with the SystemVerilog standard.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

A simple RISC V core for teaching

An AXI4 crossbar implementation in SystemVerilog

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

AMD OpenNIC Shell includes the HDL source files

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

SHA256 in (System-) Verilog / Open Source FPGA Miner

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Verilog/SystemVerilog Guide

Featherweight RISC-V implementation