A small, light weight, RISC CPU soft core
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Updated
Oct 15, 2024 - Verilog
A small, light weight, RISC CPU soft core
Bus bridges and other odds and ends
A simple, basic, formally verified UART controller
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
A utility for Composing FPGA designs from Peripherals
Simple UART controller for FPGA written in VHDL
A wishbone controlled scope for FPGA's
A collection of debugging busses developed and presented at zipcpu.com
A wishbone controlled FM transmitter hack
VexRiscV system with GDB-Server in Hardware
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
RISC-V Ibex core with Wishbone B4 interface
A caravan equipped with API for creating bus protocols in Chisel with ease.
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