A small, light weight, RISC CPU soft core
-
Updated
Nov 30, 2024 - Verilog
#
wishbone
Here are 52 public repositories matching this topic...
Bus bridges and other odds and ends
-
Updated
Jan 12, 2024 - Verilog
A simple, basic, formally verified UART controller
-
Updated
Jan 29, 2024 - Verilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
-
Updated
Nov 27, 2024 - Verilog
A utility for Composing FPGA designs from Peripherals
-
Updated
Dec 23, 2024 - C++
Simple UART controller for FPGA written in VHDL
fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback
-
Updated
Aug 7, 2021 - VHDL
A wishbone controlled scope for FPGA's
-
Updated
Jan 12, 2024 - Verilog
A collection of debugging busses developed and presented at zipcpu.com
-
Updated
Jan 18, 2024 - Verilog
A wishbone controlled FM transmitter hack
-
Updated
Jan 16, 2024 - Verilog
VexRiscV system with GDB-Server in Hardware
-
Updated
Jul 5, 2023 - VHDL
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
cpu gpio fpga uart sdcard big-endian wishbone ucosii sopc tongji-university ddr2 dynamic-pipelines openmips
-
Updated
Jun 3, 2023 - Verilog
RISC-V Ibex core with Wishbone B4 interface
-
Updated
Dec 24, 2019 - HTML
A caravan equipped with API for creating bus protocols in Chisel with ease.
-
Updated
Nov 20, 2024 - Scala
Improve this page
Add a description, image, and links to the wishbone topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the wishbone topic, visit your repo's landing page and select "manage topics."