🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Basic RISC-V CPU implementation in VHDL.

IEEE 754 single and double precision floating point library in systemverilog and vhdl

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K

IEEE 754 single precision floating point library in systemverilog and vhdl

A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores

RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)

A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores

Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

Arilla - a RISC-V based microcomputer system, with a PS2 mouse controller and 12-bit RGB SVGA graphics card, running Arilla Paint.

RISC-V pipeline CPU core implemented with verilog

基于RISC-V的单周期CPU设计 中国科学院大学研究生课程 计算机体系结构 课程大作业

Single Cycle Processor

Rival - RISC-V RV32I CPU

Configurable RISC-V core

A simple RISC-V SoC based on picorv32

An opensource ariane based SoC on aws-fpga