Bus bridges and other odds and ends
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Feb 5, 2025 - Verilog
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xilinx-vivado
Here are 51 public repositories matching this topic...
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder
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Oct 2, 2019 - Verilog
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
fpga usb rtl verilog wireshark xilinx-vivado usb-debugging usb-scanning artix-7 usb2 usb-analyzer usb-sniffer lambdaconcept-usb2sniffer-hardware
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Jun 6, 2020 - Verilog
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
calculator vhdl matrix-multiplication verilog xilinx hardware-designs xilinx-fpga low-level-programming xilinx-ise xilinx-vivado ic-design
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Aug 12, 2017 - Verilog
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
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Jun 24, 2017 - Verilog
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
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Oct 8, 2018 - Verilog
Trying to get a new skill
digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin
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Dec 31, 2024 - Verilog
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi
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Nov 21, 2017 - Verilog
Repository to store all design and testbench files for Senior Design
rtl verilog systemverilog hardware-designs testbenches xilinx-vivado hardware-security physical-unclonable-functions ring-oscillator
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Apr 16, 2020 - Verilog
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
fpga digital vhdl verilog learn xilinx digital-logic systemverilog hdl verilog-hdl xilinx-fpga xilinx-vivado digital-logic-design altera-fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 altera-quartus soc-kit altera-cyclone vhdl-verilog
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Oct 25, 2023 - Verilog
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
fpga verilog vivado prefix-tree adder xilinx-fpga xilinx-vivado zynq-7000 han-carlson brent-kung kogge-stone-adder ladner-fischer carry-look-ahead-adder ripple-carry-adder carry-save-adder prefix-adder
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Apr 13, 2021 - Verilog
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm
opencv encoding image cryptography fpga cipher image-processing verilog xilinx vivado verilog-hdl data-encryption encryption-decryption xilinx-vivado data-encryption-standard verilog-project source-coding rtldesign
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Jan 6, 2024 - Verilog
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
fpga verilog digital-signal-processing verilog-hdl audio-processing equalizer filter-design xilinx-vivado fir-filters audio-equalizer digital-system-design digital-signal-processing-filters digital-systems-design
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Dec 28, 2024 - Verilog
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
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Dec 9, 2018 - Verilog
A single cycle MIPS RISC-V CPU Core using Verilog
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Feb 12, 2023 - Verilog
100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog
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Nov 18, 2023 - Verilog
FPGA based single player game
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Aug 31, 2018 - Verilog
Suspicious Package Detection and Alert System for Public Spaces
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Apr 8, 2019 - Verilog
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