"Practice makes a man perfect"
Recently began learning RTL designing using Verilog & SystemVerilog.So, I took up a personal challenge to produce an RTL design daily and share it with you because knowledge increases by sharing. During the challenge, I am setting a target to produce 100 designs in the next 100 days which will in turn help me improve my domains of Digital Electronics Circuit and Hardware Description & Verification Language.
Also, will share my learning in the form of blogs, and also need support from you to questions and raise doubts by commenting on the LinkedIn post.
The link to recent blogs will be available in bottom section.
Link to Introductory Post: Click Here
For each day, there will be a separate folder containing the design and testbench followed by a Readme file giving a detail explanation of the working of the circuit.
| Day No. | Code Name | Link to Library | LinkedIn URL | EDA Playground Link |
|---|---|---|---|---|
| 001 | Half Adder | Link | VIEW | PLAY |
| 002 | Full Adder | Link | VIEW | PLAY |
| 003 | 3x1 Multiplexer | Link | VIEW | PLAY |
| 004 | Full Subtractor | Link | VIEW | PLAY |
| 005 | 4 Bit Comparator | Link | VIEW | PLAY |
| 006 | Clock Divider | Link | VIEW | PLAY |
| 007 | 8-3 Encoder | Link | VIEW | PLAY |
| 008 | Decimal to BCD Encoder | Link | VIEW | PLAY |
| 009 | Priority Encoder | Link | VIEW | PLAY |
| 010 | Barrel Shifter for 8-bit data | Link | VIEW | PLAY |
| 011 | Ripple Carry Adder | Link | VIEW | PLAY |
| 012 | CLA: Carry Look Ahead Adder | Link | VIEW | PLAY |
| 013 | 4-Bit: Comparator | Link | VIEW | PLAY |
| 014 | Link | |||
| 015 | Link |