OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Jul 30, 2025 - Verilog
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tcl
Here are 28 public repositories matching this topic...
Must-have verilog systemverilog modules
spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver
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Apr 8, 2025 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jul 31, 2025 - Verilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
fsm mips tcl labs verilog alu hse modelsim system-verilog mips-architecture quartus-prime quartus miem terasic-de10-lite terasic verilog-designs ddlm schoolmips dmk-press verilog-book
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Sep 15, 2023 - Verilog
5 Day TCL begginer to advanced training workshop by VSD
linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools
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Oct 18, 2023 - Verilog
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
script optimization polito tcl project synopsys dvs primetime voltage-scaling design-vision synopsys-dc
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Jun 9, 2021 - Verilog
✅ Formal verification of a 16-bit SIMD processor
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Feb 1, 2023 - Verilog
TCL Script automating the frontend of ASIC design
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Jun 21, 2023 - Verilog
Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model
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Jan 17, 2022 - Verilog
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor
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Jan 24, 2021 - Verilog
Basic JTAG standard implementation in Verilog and integration with a CUT
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May 9, 2025 - Verilog
Complete design of a Mini Stereo Digital Audio Processor
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Jan 3, 2019 - Verilog
Contains some TCL scriping language excercises + 2 university contests on HIgh Level Synthesis (winner contest) and Logic Level Synthesis
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Jul 10, 2021 - Verilog
ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.
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Mar 11, 2023 - Verilog
IR drop analysis is a critical step in digital design, focusing on the potential difference (voltage drop) between two points in a conducting wire due to its resistance. This phenomenon, described by Ohm's Law (V=IR), can significantly impact the performance of integrated circuits (IC).
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Jan 26, 2025 - Verilog
TCL Script to automate the generation of Pre-layout QoR results
linux open-source tcl synthesis yosys hardware-description-language static-timing-analysis tcl-procedures opentimer
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Jun 30, 2025 - Verilog
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