Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
script
optimization
polito
tcl
project
synopsys
dvs
primetime
voltage-scaling
design-vision
synopsys-dc
-
Updated
Jun 9, 2021 - Verilog