Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs

Dynamic Power Management (DPM) for a Power State Machine (PSM) written in C. Image processing techniques for reducing power consumption in OLED displays. Simulation of an IoT device modeled with Simulink® and scripting with MATLAB®.

Experimental study and analysis on the effect of aggressive voltage underscaling on the reliability of COTS FPGAs: https://ieeexplore.ieee.org/abstract/document/8574581/