quartus-prime

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Here are 39 public repositories matching this topic...

RomeoMe5 / DDLM

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Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

robseb / HPS2FPGAmapping

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SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

Updated Jun 9, 2021
Verilog

ItzzInfinity / 100-days-of-RTL

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Trying to get a new skill

digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin

Updated Dec 31, 2024
Verilog

MinatsuT / CYC1000_SDRAM

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A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000

Updated Jul 8, 2021
Verilog

egk696 / EDAC_SDRAM_Controller

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Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

fpga vhdl embedded-systems vivado fault-tolerant quartus-prime sdram sdram-controller cots-sdram

Updated Oct 30, 2017
Verilog

Nathen-Smith / FPGA-super-mario-bros

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FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

systemverilog fpga-soc quartus-prime nios2

Updated Dec 16, 2021
Verilog

pa-tiq / vending_machine

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fpga verilog quartus-prime quartus de10nano de10-lite de10-nano verilog-project quartus-18-1

Updated Jul 14, 2019
Verilog

tharinduSamare / Multicore_processor_verilog_design

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This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.

fpga simulation verilog modelsim quartus-prime

Updated Jan 8, 2022
Verilog

addisonElliott / LogiFindFPGATest

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This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

fpga verilog altera buzzer uart-verilog verilog-hdl 7-segment ir-receiver quartus-prime logifind nec-verilog cyclone-iv ep4ce6e22c8n pl2303 easyfpga

Updated Sep 10, 2019
Verilog

pandyah5 / ECE241_Verilog

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This repo contains all the Verilog HDL files that I made during the course.

verilog logisim verilog-hdl quartus-prime

Updated Jan 25, 2021
Verilog

RomeoMe5 / SystemGenerator-FPGA-Marsohod.org-schoolMIPS

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CAD for automatically configuring FPGA "Marsohod"

python fpga verilog hse system-verilog quartus-prime quartus miem system-generator

Updated May 1, 2023
Verilog

MohamedHussein27 / RISC-V-Single-Cycle-Implementation

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This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

vivado computer-architecture digital-design quartus-prime verilog-project rtl-design

Updated Jan 1, 2025
Verilog

realchonk / quartus-make

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This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.

template makefile makefile-template template-project quartus-prime quartus de10-lite

Updated May 28, 2022
Verilog

SamanKhamesian / Special-Purpose-Processor

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This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)

fpga state-machine controller processor vhdl gcm lcm quartus-prime de2-115