VeeR EH1 core

VeeR EL2 Core

An AXI4 crossbar implementation in SystemVerilog

DUTH RISC-V Superscalar Microprocessor

32-bit 5-stage pipelined RISC-V processor in SystemVerilog

DUTH RISC-V Microprocessor

Arquivos base para o projeto da disciplina Infraestrutura de Hardware (IF674) no CIn-UFPE.

Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.

Simple RISC-V Pipelined processor implemented on SystemVerilog.

CompactRISC (CR16) CPU (with an assembler) for the Computer Design Laboratory ECE 3710 class at The University of Utah

Minimalistic RV32I RISC-V Processor in System Verilog

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

Processor with 11 operation codes based on RISC V

A tiny 8 bit RISC ISA for on-chip/on-FPGA management purposes

Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.

It's a simple verilog based MIPS microarchitecture hardware design.

Final project for the class "Digital Design with Verilog and SystemVerilog"

A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).

This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.

An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.