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May 3, 2024 - Verilog
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riscvprocessor
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This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.
cpu fpga simulation processor riscv verilog assembly-language vivado systemverilog alu risc-v registers fpga-programming riscvprocessor
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Updated
Mar 2, 2025 - SystemVerilog
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