🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A Forth CPU and System on a Chip, based on the J1, written in VHDL

A simple RISC-V processor for use in FPGA designs.

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

HARV - HArdened Risc-V

Custom 64-bit pipelined RISC processor

Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs

An optimized pipelined MIPS CPU written in VHDL

Dual-core 16-bit RISC processor

Repository for RISC-V Unicycle Processor Implementation in VHDL and Course Material for 'Organization and Architecture of Computers' at UnB (2023/2)

A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

MIPS Pipelined CPU simulation using VHDL language

An 8-bit processor in VHDL based on a simple instruction set

A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.

A VHDL implementation of the Minimal Machine processor taught at the Karlsruhe Institute of Technology.

A pedagogical processor on FPGA, developed at NIIT University.

8-bit MISC processor with pipelining