HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

16 bit serial multiplier in SystemVerilog

Synthesizable SystemVerilog IP-Core of the I2S Receiver

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

Pulse Width Modulator programmed through an Advanced Peripheral Bus interface

UVM Test bench for a 8-bit ALU

Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board

RISC-V five stage pipline CPU

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

A systemverilog implementation of the data structures: priority queue, queue and stack

This testbench is based on SV and UVM Class based to verify Verilog HDL Design

Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

An FPGA-based Chess Engine and TPU

Verilog Codes for various Design

Multiple DUT with parallel stimulus

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.