Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

An FPGA implementation of Cummings' Asynchronous FIFO

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage fo

Uvod u UVM verifikaciju, prepravljena hijerarhija i prekucani kodovi sa youtube snimka, osnovne akademske studije

Verification of D-FF using UVM on EDA playground

in this repo will continue with rtl codes for implementation and verification of the designing, and 100 percentage of coverage model. various design using system verilog in questa and vcs and digital compiler.

APB verification based on Universal verification Method

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

BDD Gherkin implementation in native SystemVerilog, based on UVM.

1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE &Burst READ,WRITE with different burst lengths. 4)Generated functional and code coverage for the RTL verification sign-off. Skills

Moore.io Demo Project

Implement verification for APB interface and I2C protocol using UVM library

RTL detects a packet and performs LED on/off based on command bytes in packet. It has a serial TX/RX bus to communicate. It drives RX with TX bytes after link_stable is achieved(Align Markers detection). Send 5 successive AMs to assert link_stable.

Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.