A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
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Jul 24, 2025 - SystemVerilog
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rtl-design
Here are 9 public repositories matching this topic...
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy
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Nov 6, 2022 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification
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Nov 16, 2024 - SystemVerilog
Verification of D-FF using UVM on EDA playground
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Nov 19, 2023 - SystemVerilog
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level
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Jun 19, 2025 - SystemVerilog
A collection of systemverilog designs implemented on AMD Vivado tool
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Jun 26, 2025 - SystemVerilog
Processor Design of RV32I 5-Stage Pipelined CPU
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Jul 4, 2024 - SystemVerilog
A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
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Aug 9, 2025 - SystemVerilog
Processor Design of RV32I Single Cycle CPU
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Apr 28, 2024 - SystemVerilog
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