x mega menu is repsonsive mega menu based on vannilajs
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Aug 9, 2024 - JavaScript
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rtl-design
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A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router
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Sep 3, 2025 - JavaScript
Javascript Extension that changes the UI of a website from LTR to RTL
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Dec 18, 2024 - JavaScript
Single-page application of programming courses using React with a panel and login page
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Jun 2, 2024 - JavaScript
🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.
coverage fsm assertions verilog vcs synthesis systemverilog hardware-designs fifo vlsi questasim uvm digital-design functional-verification rtl-design uvm-testbench packet-router
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Oct 2, 2025 - JavaScript
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