VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

Pre and Post Synthesis Simulation of a Design VSDMemSOC

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

VSDMemSOC Implementation flow:: RTL2GDSII

Complete RTL to GDSII flow of a picorv32a core

Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language. We can also generate or report power dissipated by design. MMMC is performed