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Achievements

Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx2Achievement: Starstruck

Highlights

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Organizations

@AUCOHL @AUTOPIA-OS

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kanndil/README.md

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I'm Youssef Kandil (Kanndil)

I am Youssef Kandil a TinyMl engineer at Efabless Corporation. Previously a Computer Engineering student, research assistant, and teaching assistant in the Computer Science and Engineering Department at the The American University in Cairo. My research interests include but are not limited to Resource-Constrained Machine Learning and Computer Vision, Electronic Design Automation (EDA), Real-Time Operating Systems (RTOS), Software/Hardware Co-design and ASIC Machine Learning Acceleration.

Projects

Here are some of my key projects:

  • ❄️ Lighter ❄️: An automatic clock gating utility. Dynamic power reduction tool for open-source standard cell libraries. Check it out

  • 🧪 PodemQuest 🧪: A Google Summer of Code 2024 (GSoC24) project, focused on implementing the Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG). Check it out, Check GH Repo

  • 🏎️ AUTOPIA 🏎️: My Bachelor's thesis project in collaboration with Siemens. An AUTOSAR-compliant MultiCore Operating System. Check it out

  • 🎧 KWS MFCC Optimizer 🎧: Enhancing the Mel-Frequency Cepstral Coefficients algorithm for efficient embedded audio machine learning applications.

Publications

  • Youssef Kandil and Mohammed Shalan, Efficient MFCC Computation for Keyword Spotting on Embedded Systems: Optimization Techniques and Performance Analysis. Accepted for presentation at the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2025), Bordeaux, France, April 28–30, 2025.

  • Youssef Kandil and Mohamed Shalan, Lighter: An Open-Source Automatic Clock Gating Tool for Dynamic Power Reduction in ASIC. Presented at the Workshop on Open Source EDA Technologies (WOSET), 2024. https://openreview.net/forum?id=tNriFilLTO

📫 How to reach me

Personal Email: youssefkandil@aucegypt.edu

Github Overview 📈

kanndil's Contribution


Connect with me

ykanndil youssef-kandil-195638216

Pinned Loading

  1. AUCOHL/Lighter AUCOHL/Lighter Public

    An automatic clock gating utility

    Verilog 45 5

  2. AUTOPIA-OS/MultiCore-OS AUTOPIA-OS/MultiCore-OS Public

    C 9 1

  3. PathView PathView Public

    An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

    HTML 3 1

  4. detr-tensorflow detr-tensorflow Public

    Forked from Visual-Behavior/detr-tensorflow

    Tensorflow implementation of DETR : Object Detection with Transformers

    Jupyter Notebook

  5. chipsalliance/yosys-f4pga-plugins chipsalliance/yosys-f4pga-plugins Public

    Plugins for Yosys developed as part of the F4PGA project.

    Verilog 82 47

  6. PodemQuest PodemQuest Public

    Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).

    Python