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ubyhzargam / OpenSTA

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Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language. We can also generate or report power dissipated by design. MMMC is performed

electronics hdl vlsi sta opensta veilog
  • Updated Dec 4, 2024
  • Verilog

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