Verilog Implementation of Run Length Encoding for RGB Image Compression

Router 1 x 3 verilog implementation

FPGA Guide

RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga

ES-203 Computer Organization & Architecture CNN on FPGA board

⚡️Code release for Accelerating CNNs on FPGA [Published in Research in Intelligent and Computing in Engineering 2020]

UART - RTL Design and Verification

My experiments with Nexys4 DDR Artix-7 FPGA Board

Collection of my projects that was made as a part of Warsaw University FPGA course

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

Vertex 6 FPGA GTx Transciever Simulation in Xilinx ISE using Xilinx IP Core

This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals requ…

booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product

🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Simple car parking system in Verilog

Custom graphics driver using Verilog on Xilinx FPGA platform.

Impement a simple stopwatch on an FPGA. There is an added goal of making as many modules paramterized as possible and sticking to structural code as much as possible.

Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.