chili-chips-ba / openCologne Star 61 Code Issues Pull requests Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com design embedded fpga hls digital pcb rtl systemverilog soc risc-v gatemate colognechip Updated Mar 26, 2025 Verilog
tmeissner / gatemate_experiments Star 15 Code Issues Pull requests Experiments with Cologne Chip's GateMate FPGA architecture fpga vhdl verilog ghdl yosys gatemate Updated Nov 16, 2023 VHDL
fm4dd / gatemate-riscv Star 12 Code Issues Pull requests RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga verilog risc-v fpga-programming gatemate Updated Feb 26, 2025 Verilog
fm4dd / gm-proto-e1 Star 6 Code Issues Pull requests prototyping board for the GateMate FPGA evaluation board E1 fpga prototyping pcb-design gatemate Updated Feb 18, 2024 Verilog
fm4dd / gm-study-e1 Star 2 Code Issues Pull requests EE education board for the GateMate FPGA evaluation board E1 education fpga pcb-design gatemate Updated Mar 26, 2023
fm4dd / gm-study-max Star 0 Code Issues Pull requests EE education board for the GateMate FPGA evaluation board E1 education fpga pcb-design gatemate Updated Apr 30, 2023 Verilog