Bind Verilog path with EICG_wrapper #2969
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sequencer
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Apr 28, 2022
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See #1981 (comment)
I personally wanna have this PR. So maybe another trade-off is providing an CDE configuration and set EICG_wrapper to empty by default to resolve @aswaterman's concern.
sequencer
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May 11, 2022
aswaterman
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sequencer
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May 12, 2022
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Thanks @aswaterman :) |
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I found the EICG_wrapper.v file was not copied to the build directory automatically, the original flow works because it uses rc_resource_dir as the include path.