fix for chipsalliance/rocket-chip#2969

readme.md

@@ -78,18 +78,19 @@ then open by your favorite IDE, which supports [BSP](https://build-server-protoc
 Philosophy of this repository is **fast break and fast fix**.
 This repository always tracks remote developing branches, it may need some patches to work, `make patch` will append below in sequence:
 <!-- BEGIN-PATCH -->
-chisel3 https://github.com/chipsalliance/chisel3/pull/2515  
 cva6-wrapper https://github.com/ucb-bar/cva6-wrapper/pull/15  
 rocket-chip https://github.com/chipsalliance/rocket-chip/pull/2968  
-rocket-chip https://github.com/chipsalliance/rocket-chip/pull/2810  
+rocket-chip https://github.com/chipsalliance/rocket-chip/pull/2986  
 block-inclusivecache-sifive https://github.com/sifive/block-inclusivecache-sifive/pull/22  
 chipyard https://github.com/ucb-bar/chipyard/pull/1160  
 fpga-shells https://github.com/sifive/fpga-shells/pull/162  
 fpga-shells https://github.com/sifive/fpga-shells/pull/168  
+fpga-shells https://github.com/sifive/fpga-shells/pull/169
 riscv-sodor https://github.com/ucb-bar/riscv-sodor/pull/72  
 riscv-boom https://github.com/riscv-boom/riscv-boom/pull/600  
 riscv-boom https://github.com/riscv-boom/riscv-boom/pull/601  
 sifive-blocks https://github.com/sifive/sifive-blocks/pull/176  
+sifive-blocks https://github.com/sifive/sifive-blocks/pull/177
 rocket-dsp-utils https://github.com/ucb-bar/rocket-dsp-utils/pull/6  
 dsptools https://github.com/ucb-bar/dsptools/pull/240  
 <!-- END-PATCH -->

sanitytests/rocketchip/resources/vsrc/EICG_wrapper.v

@@ -0,0 +1,20 @@
+/* verilator lint_off UNOPTFLAT */
+
+module EICG_wrapper(
+  output out,
+  input en,
+  input test_en,
+  input in
+);
+
+  reg en_latched /*verilator clock_enable*/;
+
+  always @(*) begin
+     if (!in) begin
+        en_latched = en || test_en;
+     end
+  end
+
+  assign out = en_latched && in;
+
+endmodule

sanitytests/rocketchip/src/TestBootRom.scala → sanitytests/rocketchip/src/TestConfig.scala

@@ -2,10 +2,12 @@ package sanitytests.rocketchip
 
 import chipsalliance.rocketchip.config.Config
 import freechips.rocketchip.devices.tilelink.BootROMLocated
+import freechips.rocketchip.util.ClockGateModelFile
 import os._
 
-class TestBootRom
+class TestConfig
     extends Config((site, here, up) => {
+      case ClockGateModelFile => Some("/vsrc/EICG_wrapper.v")
       case BootROMLocated(x) =>
         up(BootROMLocated(x), site).map(_.copy(contentFileName = {
           val tmp = os.temp.dir()

sanitytests/rocketchip/src/VerilatorTest.scala

@@ -16,7 +16,7 @@ object VerilatorTest extends TestSuite {
   val tests = Tests {
     test("build TestHarness emulator") {
       val testHarness = classOf[freechips.rocketchip.system.TestHarness]
-      val configs = Seq(classOf[TestBootRom], classOf[freechips.rocketchip.system.DefaultConfig])
+      val configs = Seq(classOf[TestConfig], classOf[freechips.rocketchip.system.DefaultConfig])
       val emulator = TestHarness(testHarness, configs, Some(outputDirectory)).emulator
       test("build hello") {
         os.proc(