Merge pull request #2969 from riscv-zju/master

Bind Verilog path with EICG_wrapper

src/main/scala/subsystem/Configs.scala

@@ -336,6 +336,10 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
   case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile))
 })
 
+class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => {
+  case ClockGateModelFile => Some(file)
+})
+
 class WithSynchronousRocketTiles extends Config((site, here, up) => {
   case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
     r.copy(crossingType = SynchronousCrossing())

src/main/scala/util/ClockGate.scala

@@ -3,17 +3,29 @@
 package freechips.rocketchip.util
 
 import chisel3._
+import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
 import freechips.rocketchip.config.{Field, Parameters}
 
+import java.nio.file.{Files, Paths}
+
 case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper)
+case object ClockGateModelFile extends Field[Option[String]](None)
 
-abstract class ClockGate extends BlackBox {
+abstract class ClockGate extends BlackBox
+  with HasBlackBoxResource with HasBlackBoxPath {
   val io = IO(new Bundle{
     val in = Input(Clock())
     val test_en = Input(Bool())
     val en = Input(Bool())
     val out = Output(Clock())
   })
+
+  def addVerilogResource(vsrc: String): Unit = {
+    if (Files.exists(Paths.get(vsrc)))
+      addPath(vsrc)
+    else
+      addResource(vsrc)
+  }
 }
 
 object ClockGate {
@@ -23,6 +35,8 @@ object ClockGate {
       name: Option[String] = None)(implicit p: Parameters): Clock = {
     val cg = Module(p(ClockGateImpl)())
     name.foreach(cg.suggestName(_))
+    p(ClockGateModelFile).map(cg.addVerilogResource(_))
+
     cg.io.in := in
     cg.io.test_en := false.B
     cg.io.en := en