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Bind Verilog path with EICG_wrapper #2969

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May 12, 2022
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4 changes: 4 additions & 0 deletions src/main/scala/subsystem/Configs.scala
Original file line number Diff line number Diff line change
Expand Up @@ -330,6 +330,10 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile))
})

class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => {
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case ClockGateModelFile => Some(file)
})

class WithSynchronousRocketTiles extends Config((site, here, up) => {
case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
r.copy(crossingType = SynchronousCrossing())
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16 changes: 15 additions & 1 deletion src/main/scala/util/ClockGate.scala
Original file line number Diff line number Diff line change
Expand Up @@ -3,17 +3,29 @@
package freechips.rocketchip.util

import chisel3._
import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
import freechips.rocketchip.config.{Field, Parameters}

import java.nio.file.{Files, Paths}

case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper)
case object ClockGateModelFile extends Field[Option[String]](None)
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abstract class ClockGate extends BlackBox {
abstract class ClockGate extends BlackBox
with HasBlackBoxResource with HasBlackBoxPath {
val io = IO(new Bundle{
val in = Input(Clock())
val test_en = Input(Bool())
val en = Input(Bool())
val out = Output(Clock())
})

def addVerilogResource(vsrc: String): Unit = {
if (Files.exists(Paths.get(vsrc)))
addPath(vsrc)
else
addResource(vsrc)
}
}

object ClockGate {
Expand All @@ -23,6 +35,8 @@ object ClockGate {
name: Option[String] = None)(implicit p: Parameters): Clock = {
val cg = Module(p(ClockGateImpl)())
name.foreach(cg.suggestName(_))
p(ClockGateModelFile).map(cg.addVerilogResource(_))
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cg.io.in := in
cg.io.test_en := false.B
cg.io.en := en
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