Remove Verilog delay from DPI outputs and use falling edge instead

[jackkoenig]

Verilator ignores these delays (after warning the user), so they can
result in race conditions.

This fixes an issue visible on #2617 where some assertions fire erroneously due to some optimizations Verilator makes that are incorrect due to the race conditions.

Thank you to @ernie-sifive for doing this work

Related issue:

Type of change: bug fix

Impact: no functional change

Development Phase: implementation

Release Notes

Remove Verilog delay statements from SimJTAG.v and SimDTM.v

[aswaterman]

In general, using negedge clocking on half of a ready/valid interface is functionally incorrect. It might be the case that this interface is constrained in such a way that it's OK in this case, but I don't know.

[ernie-sifive]

All checks passed on latest commit. Changed output back to posedge to confine any negedge to within the SimDTM module.

[jackkoenig]

Is there a fundamental reason why the logic needs to be different for Verilator? Why does the negedge timing work for Verilator but not VCS?

[aswaterman]

Why does the negedge timing work for Verilator but not VCS?

This is a red flag for me, too.

[aswaterman]

I haven't thought too hard about the details, but superficially, this looks good to me.

[jackkoenig]

Let me verify that this works on the 3.4 branch then hopefully we're good to go!

[jackkoenig]

It's working on the 3.4 branch!

[jackkoenig]

I believe this is right so I'm going to merge