Remove Verilog delay from DPI outputs and use falling edge instead

src/main/resources/vsrc/SimDTM.v

@@ -19,26 +19,34 @@ module SimDTM(
   input clk,
   input reset,
 
-  output        debug_req_valid,
-  input         debug_req_ready,
-  output [ 6:0] debug_req_bits_addr,
-  output [ 1:0] debug_req_bits_op,
-  output [31:0] debug_req_bits_data,
+  output reg        debug_req_valid,
+  input             debug_req_ready,
+  output reg [ 6:0] debug_req_bits_addr,
+  output reg [ 1:0] debug_req_bits_op,
+  output reg [31:0] debug_req_bits_data,
 
-  input         debug_resp_valid,
-  output        debug_resp_ready,
-  input  [ 1:0] debug_resp_bits_resp,
-  input  [31:0] debug_resp_bits_data,
+  input             debug_resp_valid,
+  output reg        debug_resp_ready,
+  input      [ 1:0] debug_resp_bits_resp,
+  input      [31:0] debug_resp_bits_data,
 
-  output [31:0] exit
+  output reg [31:0] exit
 );
 
   bit r_reset;
 
-  wire #0.1 __debug_req_ready = debug_req_ready;
-  wire #0.1 __debug_resp_valid = debug_resp_valid;
-  wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
-  wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
+  reg __debug_req_ready;
+  reg __debug_resp_valid;
+  reg [31:0] __debug_resp_bits_resp;
+  reg [31:0]  __debug_resp_bits_data;
+
+//  // Delay sending inputs to DPI to avoid race condition failure in Verilator
+//  always @(negedge clk) begin
+  assign  __debug_req_ready = debug_req_ready;
+  assign  __debug_resp_valid = debug_resp_valid;
+  assign  __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
+  assign  __debug_resp_bits_data = debug_resp_bits_data;
+//  end
 
   bit __debug_req_valid;
   int __debug_req_bits_addr;
@@ -47,12 +55,14 @@ module SimDTM(
   bit __debug_resp_ready;
   int __exit;
 
-  assign #0.1 debug_req_valid = __debug_req_valid;
-  assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
-  assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
-  assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
-  assign #0.1 debug_resp_ready = __debug_resp_ready;
-  assign #0.1 exit = __exit;
+  always @(negedge clk) begin
+    debug_req_valid <= __debug_req_valid;
+    debug_req_bits_addr <= __debug_req_bits_addr[6:0];
+    debug_req_bits_op <= __debug_req_bits_op[1:0];
+    debug_req_bits_data <= __debug_req_bits_data[31:0];
+    debug_resp_ready <= __debug_resp_ready;
+    exit <= __exit;
+  end
 
   always @(posedge clk)
   begin

src/main/resources/vsrc/SimJTAG.v

@@ -20,15 +20,15 @@ module SimJTAG #(
                    input         enable,
                    input         init_done,
 
-                   output        jtag_TCK,
-                   output        jtag_TMS,
-                   output        jtag_TDI,
-                   output        jtag_TRSTn,
+                   output reg    jtag_TCK,
+                   output reg    jtag_TMS,
+                   output reg    jtag_TDI,
+                   output reg    jtag_TRSTn,
 
                    input         jtag_TDO_data,
                    input         jtag_TDO_driven,
 
-                   output [31:0] exit
+                   output reg [31:0] exit
                    );
 
    reg [31:0]                    tickCounterReg;
@@ -51,12 +51,13 @@ module SimJTAG #(
 
    reg          init_done_sticky;
 
-   assign #0.1 jtag_TCK   = __jtag_TCK;
-   assign #0.1 jtag_TMS   = __jtag_TMS;
-   assign #0.1 jtag_TDI   = __jtag_TDI;
-   assign #0.1 jtag_TRSTn = __jtag_TRSTn;
-
-   assign #0.1 exit = __exit;
+   always @(negedge clock) begin
+     jtag_TCK   <= __jtag_TCK;
+     jtag_TMS   <= __jtag_TMS;
+     jtag_TDI   <= __jtag_TDI;
+     jtag_TRSTn <= __jtag_TRSTn;
+     exit <= __exit;
+   end
 
    always @(posedge clock) begin
       r_reset <= reset;