Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Remove Verilog delay from DPI outputs and use falling edge instead #2635

Merged
merged 4 commits into from
Sep 15, 2020
Merged

Remove Verilog delay from DPI outputs and use falling edge instead #2635

Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
da02d6f
Remove Verilog delay from DPI outputs and use falling edge instead
ernie-sifive Sep 11, 2020
ec3a554
Update src/main/resources/vsrc/SimDTM.v
jackkoenig Sep 12, 2020
6907c0a
Use separate code for Verilog vs. others
ernie-sifive Sep 13, 2020
4bf9620
Revert unnecessary split of Verilator code
ernie-sifive Sep 14, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
38 changes: 27 additions & 11 deletions src/main/resources/vsrc/SimDTM.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -35,10 +35,10 @@ module SimDTM(

bit r_reset;

wire #0.1 __debug_req_ready = debug_req_ready;
wire #0.1 __debug_resp_valid = debug_resp_valid;
wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
wire __debug_req_ready = debug_req_ready;
wire __debug_resp_valid = debug_resp_valid;
wire [31:0] __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
wire [31:0] __debug_resp_bits_data = debug_resp_bits_data;

bit __debug_req_valid;
int __debug_req_bits_addr;
Expand All @@ -47,14 +47,30 @@ module SimDTM(
bit __debug_resp_ready;
int __exit;

assign #0.1 debug_req_valid = __debug_req_valid;
assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
assign #0.1 debug_resp_ready = __debug_resp_ready;
assign #0.1 exit = __exit;
reg debug_req_valid_reg;
reg [ 6:0] debug_req_bits_addr_reg;
reg [ 1:0] debug_req_bits_op_reg;
reg [31:0] debug_req_bits_data_reg;
reg debug_resp_ready_reg;
reg [31:0] exit_reg;

always @(posedge clk)
always @(posedge clk) begin
debug_req_valid_reg <= __debug_req_valid;
debug_req_bits_addr_reg <= __debug_req_bits_addr[6:0];
debug_req_bits_op_reg <= __debug_req_bits_op[1:0];
debug_req_bits_data_reg <= __debug_req_bits_data[31:0];
debug_resp_ready_reg <= __debug_resp_ready;
exit_reg <= __exit;
end

assign debug_req_valid = debug_req_valid_reg;
assign debug_req_bits_addr = debug_req_bits_addr_reg;
assign debug_req_bits_op = debug_req_bits_op_reg;
assign debug_req_bits_data = debug_req_bits_data_reg;
assign debug_resp_ready = debug_resp_ready_reg;
assign exit = exit_reg;

always @(negedge clk)
begin
r_reset <= reset;
if (reset || r_reset)
Expand Down