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Remove Verilog delay from DPI outputs and use falling edge instead #2635

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merged 4 commits into from
Sep 15, 2020
Merged

Remove Verilog delay from DPI outputs and use falling edge instead #2635

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da02d6f
Remove Verilog delay from DPI outputs and use falling edge instead
ernie-sifive Sep 11, 2020
ec3a554
Update src/main/resources/vsrc/SimDTM.v
jackkoenig Sep 12, 2020
6907c0a
Use separate code for Verilog vs. others
ernie-sifive Sep 13, 2020
4bf9620
Revert unnecessary split of Verilator code
ernie-sifive Sep 14, 2020
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28 changes: 28 additions & 0 deletions src/main/resources/vsrc/SimDTM.v
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,32 @@ module SimDTM(
bit __debug_resp_ready;
int __exit;

`ifdef VERILATOR
reg debug_req_valid_reg;
reg [ 6:0] debug_req_bits_addr_reg;
reg [ 1:0] debug_req_bits_op_reg;
reg [31:0] debug_req_bits_data_reg;
reg debug_resp_ready_reg;
reg [31:0] exit_reg;

always @(posedge clk) begin
debug_req_valid_reg <= __debug_req_valid;
debug_req_bits_addr_reg <= __debug_req_bits_addr[6:0];
debug_req_bits_op_reg <= __debug_req_bits_op[1:0];
debug_req_bits_data_reg <= __debug_req_bits_data[31:0];
debug_resp_ready_reg <= __debug_resp_ready;
exit_reg <= __exit;
end

assign debug_req_valid = debug_req_valid_reg;
assign debug_req_bits_addr = debug_req_bits_addr_reg;
assign debug_req_bits_op = debug_req_bits_op_reg;
assign debug_req_bits_data = debug_req_bits_data_reg;
assign debug_resp_ready = debug_resp_ready_reg;
assign exit = exit_reg;

always @(negedge clk)
`else
assign #0.1 debug_req_valid = __debug_req_valid;
assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
Expand All @@ -55,6 +81,8 @@ module SimDTM(
assign #0.1 exit = __exit;

always @(posedge clk)
`endif

begin
r_reset <= reset;
if (reset || r_reset)
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