Merge pull request sysprog21#10 from feathertw/fix_csrrwi_

Fix csrrwi instruction behavior
vestata · Jan 6, 2022 · 91232c2 · 91232c2
2 parents fa38fc5 + 54061df
commit 91232c2
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv.c b/riscv.c
@@ -633,7 +633,7 @@ static bool op_system(struct riscv_t *rv, uint32_t inst)
         break;
     }
     case 5: {  // CSRRWI
-        uint32_t tmp = csr_csrrc(rv, csr, rv->X[rs1]);
+        uint32_t tmp = csr_csrrw(rv, csr, rs1);
         rv->X[rd] = rd ? tmp : rv->X[rd];
         break;
     }