Fix CSRRWI instruction behavior according to RISC-V spec

Refer to RISC-V Unprivileged ISA Version 20191213 9.1 CSR Instructions

----------------------------------------------------------------------
| 31                 20|19       15|14       12|11       7|6        0|
|         csr          |    rs1    |   funct3  |    rd    |  opcode  |
|     source/dest      | uimm[4:0] |   CSRRWI  |   dest   |  SYSTEM  |
----------------------------------------------------------------------

CSRRWI behavior likes below and it needs to work atomically

x[rd] = CSRs[csr]; CSRs[csr] = uimm

The uimm is equal to rs1's index, instead of rs1's register value

Close sysprog21#7

riscv.c

@@ -633,7 +633,7 @@ static bool op_system(struct riscv_t *rv, uint32_t inst)
         break;
     }
     case 5: {  // CSRRWI
-        uint32_t tmp = csr_csrrc(rv, csr, rv->X[rs1]);
+        uint32_t tmp = csr_csrrw(rv, csr, rs1);
         rv->X[rd] = rd ? tmp : rv->X[rd];
         break;
     }