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riscv.c 中 op_system 的 CSRRWI 處理是否寫錯了? #7
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feathertw
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…g21#7) According to RISC-V Unprivileged ISA Version 20191213- 9.1 CSR Instructions ----------------------------------------------------------------------- | 31 20|19 15|14 12|11 7|6 0| | csr | rs1 | funct3 | rd | opcode | | source/dest | uimm[4:0] | CSRRWI | dest | SYSTEM | ----------------------------------------------------------------------- CSRRWI behavior likes below and it needs to work atomically x[rd] = CSRs[csr]; CSRs[csr] = uimm The uimm value is equal to the rs1's index, instead of the rs1's register value Close sysprog21#7
feathertw
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…g21#7) Refer to RISC-V Unprivileged ISA Version 20191213 9.1 CSR Instructions ---------------------------------------------------------------------- | 31 20|19 15|14 12|11 7|6 0| | csr | rs1 | funct3 | rd | opcode | | source/dest | uimm[4:0] | CSRRWI | dest | SYSTEM | ---------------------------------------------------------------------- CSRRWI behavior likes below and it needs to work atomically x[rd] = CSRs[csr]; CSRs[csr] = uimm The uimm is equal to rs1's index, instead of rs1's register value Close sysprog21#7
vestata
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Jan 24, 2025
Refer to RISC-V Unprivileged ISA Version 20191213 9.1 CSR Instructions ---------------------------------------------------------------------- | 31 20|19 15|14 12|11 7|6 0| | csr | rs1 | funct3 | rd | opcode | | source/dest | uimm[4:0] | CSRRWI | dest | SYSTEM | ---------------------------------------------------------------------- CSRRWI behavior likes below and it needs to work atomically x[rd] = CSRs[csr]; CSRs[csr] = uimm The uimm is equal to rs1's index, instead of rs1's register value Close sysprog21#7
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