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riscv.c 中 op_system 的 CSRRWI 處理是否寫錯了? #7

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ccckmit opened this issue Aug 24, 2021 · 0 comments
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riscv.c 中 op_system 的 CSRRWI 處理是否寫錯了? #7

ccckmit opened this issue Aug 24, 2021 · 0 comments
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ccckmit commented Aug 24, 2021

static bool op_system(struct riscv_t *rv, uint32_t inst)
{
#ifdef ENABLE_Zicsr
    case 1: {  // CSRRW    (Atomic Read/Write CSR)
        uint32_t tmp = csr_csrrw(rv, csr, rv->X[rs1]);
        rv->X[rd] = rd ? tmp : rv->X[rd];
        break;
    }
   // ...
    case 5: {  // CSRRWI
        uint32_t tmp = csr_csrrc(rv, csr, rv->X[rs1]); // 這裡是否應該改為 csr_csrrw(rv, csr, rv->X[rs1])
        rv->X[rd] = rd ? tmp : rv->X[rd];
        break;
    }
   // ...
}
@ccckmit ccckmit changed the title op_system 中 CSRRWI 的處理是否寫錯了? riscv.c 中 op_system 的 CSRRWI 處理是否寫錯了? Aug 24, 2021
feathertw added a commit to feathertw/rv32emu-next that referenced this issue Jan 6, 2022
…g21#7)

According to RISC-V Unprivileged ISA Version 20191213- 9.1 CSR Instructions

-----------------------------------------------------------------------
| 31                  20|19       15|14       12|11       7|6        0|
|          csr          |    rs1    |   funct3  |    rd    |  opcode  |
|      source/dest      | uimm[4:0] |   CSRRWI  |   dest   |  SYSTEM  |
-----------------------------------------------------------------------

CSRRWI behavior likes below and it needs to work atomically

x[rd] = CSRs[csr]; CSRs[csr] = uimm

The uimm value is equal to the rs1's index, instead of the rs1's register value

Close sysprog21#7
feathertw added a commit to feathertw/rv32emu-next that referenced this issue Jan 6, 2022
…g21#7)

Refer to RISC-V Unprivileged ISA Version 20191213 9.1 CSR Instructions

----------------------------------------------------------------------
| 31                 20|19       15|14       12|11       7|6        0|
|         csr          |    rs1    |   funct3  |    rd    |  opcode  |
|     source/dest      | uimm[4:0] |   CSRRWI  |   dest   |  SYSTEM  |
----------------------------------------------------------------------

CSRRWI behavior likes below and it needs to work atomically

x[rd] = CSRs[csr]; CSRs[csr] = uimm

The uimm is equal to rs1's index, instead of rs1's register value

Close sysprog21#7
@jserv jserv closed this as completed in a830817 Jan 6, 2022
vestata pushed a commit to vestata/rv32emu that referenced this issue Jan 24, 2025
Refer to RISC-V Unprivileged ISA Version 20191213 9.1 CSR Instructions

----------------------------------------------------------------------
| 31                 20|19       15|14       12|11       7|6        0|
|         csr          |    rs1    |   funct3  |    rd    |  opcode  |
|     source/dest      | uimm[4:0] |   CSRRWI  |   dest   |  SYSTEM  |
----------------------------------------------------------------------

CSRRWI behavior likes below and it needs to work atomically

x[rd] = CSRs[csr]; CSRs[csr] = uimm

The uimm is equal to rs1's index, instead of rs1's register value

Close sysprog21#7
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