Fix csrrwi instruction behavior according to risc-v spec #10
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Can you quote from RISC-V privileged instruction in git commit message? The instruction format should be mentioned and explained. You don't have to re-create the new issues. Instead, use |
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Also, append |
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I add more information into the commit log and then |
jserv
requested changes
Jan 6, 2022
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Please read this carefully: https://dev.to/thelogeshwaran/how-to-write-good-commit-messages-714
- Wrap lines at 72 characters
Don't mention "Issue #7" in the subject of git commit message.
Refer to RISC-V Unprivileged ISA Version 20191213 9.1 CSR Instructions ---------------------------------------------------------------------- | 31 20|19 15|14 12|11 7|6 0| | csr | rs1 | funct3 | rd | opcode | | source/dest | uimm[4:0] | CSRRWI | dest | SYSTEM | ---------------------------------------------------------------------- CSRRWI behavior likes below and it needs to work atomically x[rd] = CSRs[csr]; CSRs[csr] = uimm The uimm is equal to rs1's index, instead of rs1's register value Close sysprog21#7
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Thank @feathertw for contributing! |
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My pleasure! |
vestata
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to vestata/rv32emu
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Jan 24, 2025
Fix csrrwi instruction behavior
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