An FPGA design for simulating biological neurons
16 bit serial multiplier in SystemVerilog
Verification of spi protocol
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
This system manages ALU and register file operations based on commands received via UART RX. It operates across two clock domains—one for general processing and another for UART communication. Key functions include executing arithmetic, logic, and data synchronization tasks, with results sent back through UART TX
A test bench for asynchronous fifos
Verilog-Training-5-stage-Pipeline-CPU
Verilog-HDL implementation of a simple 4-bit PC.
References and supplemental material for for projects involving programming of a microfluidics array
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
This project provides a comprehensive verification framework for a synchronous single-port RAM module implemented in Verilog. The memory module is configurable with parameters for data width, memory depth, and address width. It operates synchronously with a clock signal and uses a valid-ready handshake protocol to control read and write operations.
Verilog Projects : 1) Vending Machine 2)Traffic Light Controller
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