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1. Multi-Clock-Domain-System-for-UART-Controlled-ALU-and-Register-Operations-in-Verilog Multi-Clock-Domain-System-for-UART-Controlled-ALU-and-Register-Operations-in-Verilog Public

   This system manages ALU and register file operations based on commands received via UART RX. It operates across two clock domains—one for general processing and another for UART communication. Key …

   SystemVerilog 2

2. ATMModel ATMModel Public

   I created an ATM model to to implement key banking functions such as withdrawing, depositing, and transferring funds.

   C++

3. MIPS-based-SoC-design MIPS-based-SoC-design Public

   Key Outcomes: -Improved instruction throughput with multi-stage pipelining. -Significant reduction in pipeline stalls through effective branch prediction. -Seamless hazard resolution with minimal i…

   Verilog

4. Synchronous-FIFO-verification-in-UVM Synchronous-FIFO-verification-in-UVM Public

   SystemVerilog