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verilog-hdl

Here are 539 public repositories matching this topic...

jj1and / KRD

Verilog-HDL/VHDL project

python c hdl verilog-hdl xilinx-ip

Updated Feb 24, 2021
VHDL

camalasad / Digital-Electronics-Projects

Digital Electronics Course Projects

digital electronics verilog-hdl digital-circuits multisim-simulation

Updated Jun 7, 2020
Verilog

J-StrawHat / 74LS191-counter

基于FPGA实现的74LS191（同步16进制加/减计数器）

verilog-hdl nexy4 74ls191

Updated Jul 20, 2021
Verilog

tylerfeldman321 / Crane-Game

Crane Game using Custom Pipelined Processor

arduino mechanical-engineering assembly-language verilog-hdl 3d-printing stepper-motor-control laser-cutting circuit-design pipelined-processors

Updated Sep 17, 2022
VHDL

omerbitikcioglu / gtu-homeworks

c java r cpp common-lisp prolog data-structures verilog operating-systems verilog-hdl opencv-python

Updated Sep 11, 2023
C

SagarDevAchar / endmodule

Open Source Verilog Modules

open-source module verilog adder verilog-hdl verilog-code

Updated Jan 25, 2023
Verilog

yilmaz0734 / FPGATictactoegame

In this project, we implemented a different kind of a tic tac toe board game that is played on an FPGA board using its push buttons. We used Verilog HDL to code the project and implemented a VGA interface for visualization.

game-logic fpga-soc verilog-hdl tic-tac-toe-game vga-controller vga-screen fpga-programming

Updated Jul 25, 2023
Verilog

Gurusatwik / PWM-Generator

This repository focuses on how to design a PWM Generator with variable Duty cycle

asic fpga verilog-hdl pwm-generator digitalelectronics

Updated Nov 22, 2023
Verilog

Robin329 / VerilogThings

Some exercises on verilog.

fpga verilog fpga-soc-linux verilog-hdl fpga-programming

Updated Dec 21, 2023
Verilog

gvd1248 / FPGA

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

fsm dsp vhdl verification finite-state-machine gtkwave testbench verilog-hdl digital-circuits ip-core uart-vhdl rtl-simulations

Updated Sep 5, 2024
Verilog

NeilNie / BasicSequentialLogic_Lab3

The purpose is to investigate latches, flip-flops, and registers. DA CS 603

vhdl verilog verilog-hdl

Updated Nov 12, 2018
VHDL

LuciusSchoenbaum / EE543_project

EE 543 project, Fall 2019 for Dr. Na Gong

verilog verilog-hdl

Updated Dec 4, 2019
Verilog

Sudeep-Dhurua / verilog-to-gate-level-synthesis

This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

verilog-hdl vlsi-cad rtl-synthesis

Updated Apr 11, 2021

madmaverickminion / Soil-monitoring-bot

This repository contains all the work(till task 5) of Soil Monitoring Bot theme(eYRC-2021-22).

robotics verilog-hdl quartus-prime dijkstra-shortest-path fpga-programming

Updated Mar 3, 2022
Verilog

briandallaire / portfolio

My Coding Portfolio

python c java cpp verilog-hdl embedded-c systemverilog-hdl

Updated May 3, 2022
SystemVerilog

Jayanth-sharma / FIFO-design

Designed 32-bit data Width Sync FIFO and Synchronizer.

Updated Oct 27, 2022
Verilog

gsxgoldenlegendary / codh-labs

Source of USTC CODH Experiment(Advanced Class).

verilog-hdl computer-organization

Updated Aug 23, 2022
Verilog

nekoday / ElecDesign-Contest-University-2021

Adjustable sinusoidal signal generator based on FPGA

fpga dds verilog-hdl dac

Updated Nov 15, 2023
Verilog

manuemmanuel / Gates-Verilog-HDL

This repository contains a collection of basic digital logic gates implemented in Verilog HDL (Hardware Description Language).

verilog and verilog-hdl nand or not gates nor

Updated May 14, 2024
Verilog

Erfangholiz / My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

vhdl verilog logic-gates modelsim verilog-hdl logic-circuit logical-gates quartus vhdl-code logical-circuits vhdl-examples verilog-project quartus2 verilog-code

Updated May 24, 2024
Verilog

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