A flexible framework for analyzing and transforming FPGA netlists. Official repository.
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Updated
Mar 4, 2024 - Python
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
intro to electronics & robotics
Ladder Diagram editor implementation using Qt. See: https://code.qt.io/cgit/qt/qtbase.git/tree/examples/widgets/graphicsview/diagramscene?h=5.14
A validated design database and simulation workflow software for superconducting quantum hardware
An asset which include circuit symbols for drawing schematics and block diagrams with Affinity Designer
An LTspice project which contains third-order Butterworth filters built both using an inductor and a current conveyor.
A basic USB mouse PCB based on the PAW3526D8-FJY2 Sensor.
This library is an attempt to make transistor sizing for Analog design less painful.
Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.
Demonstration of the working of Chua's Diode using the concept of Negative Impedance
A breadboard-based circuit designer and simulator written in Java
Devcontainers for Integrated-circuit design using the Viper IC design environment
Quantum Circuit Designer: A gymnasium-based set of environments for benchmarking reinforcement learning for quantum circuit design.
A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog
Vezzal is a tool flow currently built to test Netgen and Magic by providing an environment and a testcases database. It can either be used through Github Actions or as a standalone mode. It is designed and developed by following the KISS principle (Keep it Simple, Stupid) offering complete freedom for users yet keeping things simple.
Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates
Implementation of Cartesian Genetic Programming (CGP) for design of logic circuits in the form of Majority Inverter Graph (MIG)
Introductory course to Self Timed Circuits
vhdl
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