#

quartus

Here are 86 public repositories matching this topic...

MJoergen / HyperRAM

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Oct 22, 2024
VHDL

flsing / CEG2136

Computer Architecture

cpu vhdl waveform oscilloscope assembly-language altera logic-gates alu machine-language bdf quartus mif

Updated Dec 6, 2017
VHDL

alvarezpj / single-cycle-cpu

VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls

fpga vhdl quartus single-cycle de2-board altera-fpga

Updated Dec 17, 2019
VHDL

FedorChervyakov / de10lite-hello-vga

VGA demo on the Terasic DE10-Lite FPGA board

fpga makefile vga quartus de10-lite

Updated Jun 6, 2021
VHDL

janaite / fpga-de10lite-golden-top

DE10-Lite golden top

fpga vhdl quartus

Updated Jun 13, 2021
VHDL

MaorAssayag / Architecture-of-CPU-projects

VHDL , ModelSIM, Quartus, FPGA, Image Processing

fpga vhdl modelsim quartus cpu-architecture

Updated Jan 19, 2019
VHDL

dominiksalvet / pcycle

My first processor written in HDL language

Updated Aug 21, 2022
VHDL

robodhruv / digital-design

VHDL Code Dump for Digital Circuits Lab (EE214), Spring 2017

vhdl hdl digital-design quartus

Updated Feb 1, 2018
VHDL

Charlie5DH / RISC-V-Single-Cycle-uP

Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture

fpga vhdl microprocessors risc-v quartus vhdl-code

Updated Jul 24, 2020
VHDL

ChiefGokhlayeh / DT1

Digitaltechnik 1 - University of Esslingen

fpga vhdl university-project quartus

Updated Jun 16, 2019
VHDL

zorkzorkus / ZorkCores

Collection of IP-Cores for Altera FPGAs using Quartus IDE.

cpu fpga vhdl riscv quartus i2s

Updated Dec 9, 2023
VHDL

david-shmailov / CPU_task3_MIPS

We implemented a single cycle version of the MIPS CPU in VHDL code, under the simplification of 1 cycle memory delay, a reduced instruction set defined by the assignment, and 10-bit memory space. We then used the Quartus FPGA chipset to verify the design. By David Shmailov and Aviram Lachmani

design fpga mips vhdl verification mips-architecture quartus digital-architecture

Updated Aug 2, 2021
VHDL

david-shmailov / CPU_Task2_FPGA

Verification of RTL design via a Quartus FPGA chipset, Written by David Shmailov and Aviram Lachmani

design fpga vhdl verification quartus

Updated Aug 2, 2021
VHDL

FelixLuciano / Elements-of-Computing-Systems

Develop a computer from ground up. From NAND to Tetris!

vhdl simulink nand2tetris boolean-algebra quartus elements-of-computing-systems

Updated Jan 1, 2023
VHDL

LockBall / floatfixlib_VHDL1993

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

vhdl modelsim float fixed quartus de10-lite questa floatfixlib ieee-proposed

Updated Oct 25, 2023
VHDL

GSimas / EEL5105

💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC

Updated Apr 3, 2020
VHDL

yasaspeiris / VHDL-LiftSimulator

A finite state machine in VHDL modeled after an elevator

vhdl finite-state-machine altera quartus

Updated Jul 19, 2019
VHDL

ahmadsalimi / MultiCycle

Custom Multicycle DataPath Design

Updated Oct 4, 2020
VHDL

1allan / Genius

A VHDL implementation of the mini-game Genius.

vhdl genius simon quartus

Updated Jan 15, 2020
VHDL

Pedroo64 / XtrRiscv

microcontroller cpu vhdl riscv vivado lattice risc-v quartus riscv32 softcore

Updated Oct 20, 2024
VHDL

Improve this page

Add a description, image, and links to the quartus topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the quartus topic, visit your repo's landing page and select "manage topics."