Skip to content
View MJoergen's full-sized avatar

Block or report MJoergen

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
MJoergen/README.md

Hi there 👋

MJoergen | LinkedIn

Popular repositories Loading

  1. nexys4ddr nexys4ddr Public

    Various projects for the Nexys4DDR board from Digilent

    VHDL 127 14

  2. formal formal Public

    Playing around with Formal Verification of Verilog and VHDL

    Assembly 54 1

  3. mchess mchess Public

    A very simple chess engine

    C++ 52 17

  4. HyperRAM HyperRAM Public

    Portable HyperRAM controller

    VHDL 49 11

  5. C64MEGA65 C64MEGA65 Public

    Forked from sy2002/MiSTer2MEGA65

    Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core

    VHDL 32 5

  6. mchess2 mchess2 Public

    A fully functioning chess engine

    C++ 21 7