jakubcabal / spi-fpga Sponsor Star 168 Code Issues Pull requests SPI master and SPI slave for FPGA written in VHDL fpga controller vhdl accelerometer spi ghdl spi-master spi-slave cyc1000 spi-loopback spi-controller Updated Apr 24, 2021 VHDL
jakubcabal / uart-for-fpga Sponsor Star 92 Code Issues Pull requests Simple UART controller for FPGA written in VHDL fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback Updated Aug 7, 2021 VHDL
jakubcabal / rmii-firewall-fpga Sponsor Star 21 Code Issues Pull requests RMII Firewall FPGA fpga firewall vhdl ethernet wishbone-bus rmii cyc1000 Updated Dec 2, 2019 VHDL
jakubcabal / sdram-tester-fpga Sponsor Star 9 Code Issues Pull requests SDRAM Tester implemented in FPGA python fpga vhdl sdram sdram-controller cyc1000 measures-throughput sdram-tester Updated May 1, 2021 VHDL
jakubcabal / cyc1000-rsu Sponsor Star 7 Code Issues Pull requests The CYC1000 FPGA Remote System Upgrade project fpga vhdl uart rsu cyc1000 bitstream-update cyclone10lp Updated Aug 8, 2021 VHDL
DECAfpga / BBC_DemiSTify Star 1 Code Issues Pull requests BBC micro - Demistified for Deca & Neptuno. [This fork is only a mirror, not for development] fpga computers cape cyc1000 demistify 3pins mergefork Updated Jul 13, 2022 VHDL
AtlasFPGA / vt105_2023_PDP11 Star 0 Code Issues Pull requests se añaden los ficheros modificados en la creación de la terminal cyc1000 vt105 Updated Mar 2, 2023 VHDL