-
Notifications
You must be signed in to change notification settings - Fork 96
PINE64 (Allwinner A64)
Siarhei Siamashka edited this page Apr 3, 2016
·
2 revisions
ARM Cortex-A53 @1152MHz, DDR3 @672MHz
Processor : AArch64 Processor rev 4 (aarch64) processor : 0 processor : 1 processor : 2 processor : 3 Features : fp asimd aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: AArch64 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 4 Hardware : sun50iw1p1
64-bit tinymembench build:
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1232.9 MB/s (0.3%)
C copy backwards (32 byte blocks) : 1240.6 MB/s (0.4%)
C copy backwards (64 byte blocks) : 1242.1 MB/s (0.2%)
C copy : 1205.7 MB/s (1.1%)
C copy prefetched (32 bytes step) : 1211.5 MB/s (1.4%)
C copy prefetched (64 bytes step) : 1232.3 MB/s (1.6%)
C 2-pass copy : 1115.2 MB/s
C 2-pass copy prefetched (32 bytes step) : 1115.0 MB/s
C 2-pass copy prefetched (64 bytes step) : 1115.1 MB/s
C fill : 3095.9 MB/s (0.1%)
C fill (shuffle within 16 byte blocks) : 3096.3 MB/s
C fill (shuffle within 32 byte blocks) : 3096.7 MB/s
C fill (shuffle within 64 byte blocks) : 3096.4 MB/s
---
standard memcpy : 1242.9 MB/s
standard memset : 3097.3 MB/s (0.1%)
---
NEON LDP/STP copy : 1238.8 MB/s (0.7%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 871.9 MB/s (1.3%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1066.4 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 1319.2 MB/s
NEON LDP/STP copy pldl1keep (64 bytes step) : 1318.6 MB/s
NEON LD1/ST1 copy : 1240.1 MB/s (0.2%)
NEON STP fill : 3097.5 MB/s (0.1%)
NEON STNP fill : 2336.2 MB/s (0.4%)
ARM LDP/STP copy : 1245.5 MB/s (0.6%)
ARM STP fill : 3097.5 MB/s (0.1%)
ARM STNP fill : 2329.1 MB/s (1.0%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 181.1 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 174.0 MB/s
NEON LD1/ST1 copy (from framebuffer) : 47.2 MB/s
NEON LD1/ST1 2-pass copy (from framebuffer) : 46.6 MB/s
ARM LDP/STP copy (from framebuffer) : 93.2 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 91.3 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 5.9 ns / 10.0 ns
131072 : 9.1 ns / 13.9 ns
262144 : 10.7 ns / 15.5 ns
524288 : 12.9 ns / 18.3 ns
1048576 : 92.9 ns / 143.2 ns
2097152 : 135.2 ns / 184.2 ns
4194304 : 164.2 ns / 206.6 ns
8388608 : 179.4 ns / 216.9 ns
16777216 : 188.7 ns / 223.6 ns
33554432 : 193.9 ns / 227.7 ns
67108864 : 196.8 ns / 230.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 5.9 ns / 10.1 ns
131072 : 9.1 ns / 14.2 ns
262144 : 10.7 ns / 15.9 ns
524288 : 12.9 ns / 18.9 ns
1048576 : 92.9 ns / 143.3 ns
2097152 : 135.0 ns / 184.1 ns
4194304 : 156.2 ns / 197.9 ns
8388608 : 166.8 ns / 203.2 ns
16777216 : 172.1 ns / 205.3 ns
33554432 : 174.7 ns / 206.3 ns
67108864 : 176.2 ns / 206.8 ns
32-bit tinymembench build:
tinymembench v0.4 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1208.7 MB/s (0.9%)
C copy backwards (32 byte blocks) : 1196.3 MB/s (0.4%)
C copy backwards (64 byte blocks) : 1219.1 MB/s (0.7%)
C copy : 1223.8 MB/s (0.6%)
C copy prefetched (32 bytes step) : 1280.9 MB/s
C copy prefetched (64 bytes step) : 1282.5 MB/s
C 2-pass copy : 1091.1 MB/s
C 2-pass copy prefetched (32 bytes step) : 1171.3 MB/s
C 2-pass copy prefetched (64 bytes step) : 1163.3 MB/s
C fill : 3080.1 MB/s (0.1%)
C fill (shuffle within 16 byte blocks) : 3079.9 MB/s
C fill (shuffle within 32 byte blocks) : 3080.2 MB/s
C fill (shuffle within 64 byte blocks) : 3079.5 MB/s
---
standard memcpy : 1227.1 MB/s (0.4%)
standard memset : 3032.3 MB/s
---
NEON read : 1640.2 MB/s (0.2%)
NEON read prefetched (32 bytes step) : 1824.7 MB/s
NEON read prefetched (64 bytes step) : 1824.8 MB/s
NEON read 2 data streams : 1473.6 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 1766.9 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 1766.4 MB/s
NEON copy : 1231.5 MB/s (0.2%)
NEON copy prefetched (32 bytes step) : 1285.0 MB/s
NEON copy prefetched (64 bytes step) : 1285.8 MB/s
NEON unrolled copy : 1226.6 MB/s
NEON unrolled copy prefetched (32 bytes step) : 1307.5 MB/s
NEON unrolled copy prefetched (64 bytes step) : 1307.2 MB/s
NEON copy backwards : 1230.5 MB/s (0.1%)
NEON copy backwards prefetched (32 bytes step) : 1279.0 MB/s
NEON copy backwards prefetched (64 bytes step) : 1279.1 MB/s
NEON 2-pass copy : 1111.7 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 1177.0 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 1178.4 MB/s
NEON unrolled 2-pass copy : 1085.7 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1131.9 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1146.5 MB/s
NEON fill : 3080.8 MB/s (0.1%)
NEON fill backwards : 3080.5 MB/s
VFP copy : 1230.3 MB/s (0.2%)
VFP 2-pass copy : 1089.8 MB/s
ARM fill (STRD) : 3031.7 MB/s
ARM fill (STM with 8 registers) : 3077.8 MB/s
ARM fill (STM with 4 registers) : 3073.3 MB/s
ARM copy prefetched (incr pld) : 1282.9 MB/s
ARM copy prefetched (wrap pld) : 1268.8 MB/s
ARM 2-pass copy prefetched (incr pld) : 1126.3 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1121.8 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON read (from framebuffer) : 47.3 MB/s
NEON copy (from framebuffer) : 45.5 MB/s
NEON 2-pass copy (from framebuffer) : 46.5 MB/s
NEON unrolled copy (from framebuffer) : 46.7 MB/s
NEON 2-pass unrolled copy (from framebuffer) : 46.3 MB/s
VFP copy (from framebuffer) : 331.7 MB/s
VFP 2-pass copy (from framebuffer) : 305.8 MB/s
ARM copy (from framebuffer) : 155.4 MB/s
ARM 2-pass copy (from framebuffer) : 165.6 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 5.9 ns / 10.0 ns
131072 : 9.1 ns / 14.0 ns
262144 : 10.7 ns / 15.5 ns
524288 : 12.7 ns / 17.7 ns
1048576 : 92.8 ns / 143.2 ns
2097152 : 134.9 ns / 184.4 ns
4194304 : 163.5 ns / 207.1 ns
8388608 : 178.6 ns / 217.6 ns
16777216 : 187.5 ns / 223.7 ns
33554432 : 192.8 ns / 228.0 ns
67108864 : 195.8 ns / 230.7 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 5.9 ns / 10.0 ns
131072 : 9.1 ns / 14.0 ns
262144 : 10.7 ns / 15.6 ns
524288 : 12.6 ns / 17.8 ns
1048576 : 92.7 ns / 142.6 ns
2097152 : 134.7 ns / 184.3 ns
4194304 : 155.8 ns / 198.4 ns
8388608 : 166.4 ns / 203.8 ns
16777216 : 171.6 ns / 206.0 ns
33554432 : 174.2 ns / 206.9 ns
67108864 : 175.4 ns / 207.4 ns
Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.
tinymembench v0.4.9 (simple benchmark for memory thr
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2949.7 MB/s (3.8%)
C copy backwards (32 byte blocks) : 3011.8 MB/s
C copy backwards (64 byte blocks) : 3029.2 MB/s
C copy : 3642.2 MB/s (4.1%)
C copy prefetched (32 bytes step) : 3824.4 MB/s (0.3%)
C copy prefetched (64 bytes step) : 3825.3 MB/s (0.4%)
C 2-pass copy : 2726.2 MB/s
C 2-pass copy prefetched (32 bytes step) : 2902.6 MB/s (2.5%)
C 2-pass copy prefetched (64 bytes step) : 2928.3 MB/s (0.3%)
C fill : 8541.0 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 8518.5 MB/s (2.1%)
C fill (shuffle within 32 byte blocks) : 8537.1 MB/s (0.1%)
C fill (shuffle within 64 byte blocks) : 8528.7 MB/s (0.2%)
---
standard memcpy : 3558.8 MB/s
standard memset : 8520.2 MB/s
---
NEON LDP/STP copy : 3633.9 MB/s (4.2%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 1451.0 MB/s (0.3%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1450.9 MB/s (0.5%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 3882.5 MB/s (3.9%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 3884.0 MB/s (0.4%)
NEON LD1/ST1 copy : 3630.8 MB/s (0.3%)
NEON STP fill : 8537.8 MB/s
NEON STNP fill : 8544.9 MB/s (1.7%)
ARM LDP/STP copy : 3635.8 MB/s (0.3%)
ARM STP fill : 8544.8 MB/s (0.1%)
ARM STNP fill : 8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 766.0 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 688.8 MB/s
NEON LD1/ST1 copy (from framebuffer) : 770.6 MB/s (0.1%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 681.3 MB/s (0.3%)
ARM LDP/STP copy (from framebuffer) : 766.1 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 689.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.1 ns / 0.1 ns
32768 : 1.7 ns / 2.9 ns
65536 : 6.4 ns / 9.5 ns
131072 : 9.6 ns / 12.3 ns
262144 : 13.7 ns / 17.0 ns
524288 : 15.8 ns / 19.7 ns
1048576 : 17.3 ns / 22.1 ns
2097152 : 42.1 ns / 64.2 ns
4194304 : 98.5 ns / 138.1 ns
8388608 : 143.9 ns / 186.3 ns
16777216 : 167.2 ns / 211.2 ns
33554432 : 180.1 ns / 227.1 ns
67108864 : 200.0 ns / 260.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.4 ns / 9.4 ns
131072 : 9.5 ns / 12.2 ns
262144 : 11.2 ns / 13.1 ns
524288 : 12.1 ns / 13.5 ns
1048576 : 12.8 ns / 13.6 ns
2097152 : 27.0 ns / 33.0 ns
4194304 : 90.6 ns / 127.8 ns
8388608 : 123.9 ns / 153.8 ns
16777216 : 139.5 ns / 161.2 ns
33554432 : 147.2 ns / 163.6 ns
67108864 : 154.0 ns / 167.6 ns