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Microsoft Surface Pro X (Microsoft SQ1 Qualcomm SC8180X)

Bingxing Wang edited this page Feb 25, 2020 · 1 revision

Running Debian 10 in Hyper-V virtual machine, with 8 vCPU allocated. Memory clocks at 2133MHz.

Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              8
On-line CPU(s) list: 0-7
Thread(s) per core:  1
Core(s) per socket:  8
Socket(s):           1
Vendor ID:           Qualcomm
Model:               14
Stepping:            0xd
BogoMIPS:            38.40
Flags:               fp asimd aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp

Compiler flags:

-O3 -march=armv8.2-a -mtune=cortex-a75.cortex-a55

==========================================================================
== Memory bandwidth tests                                               ==
==                                                                      ==
== Note 1: 1MB = 1000000 bytes                                          ==
== Note 2: Results for 'copy' tests show how many bytes can be          ==
==         copied per second (adding together read and writen           ==
==         bytes would have provided twice higher numbers)              ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
==         to first fetch data into it, and only then write it to the   ==
==         destination (source -> L1 cache, L1 cache -> destination)    ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in    ==
==         brackets                                                     ==
==========================================================================

 C copy backwards                                     :  12442.3 MB/s (5.8%)
 C copy backwards (32 byte blocks)                    :  12567.4 MB/s (2.9%)
 C copy backwards (64 byte blocks)                    :  12717.2 MB/s (1.8%)
 C copy                                               :  13679.0 MB/s (1.4%)
 C copy prefetched (32 bytes step)                    :  14011.8 MB/s (1.2%)
 C copy prefetched (64 bytes step)                    :  13911.5 MB/s (0.5%)
 C 2-pass copy                                        :   5345.9 MB/s (10.9%)
 C 2-pass copy prefetched (32 bytes step)             :   8757.7 MB/s (4.0%)
 C 2-pass copy prefetched (64 bytes step)             :   8025.0 MB/s (1.7%)
 C fill                                               :  32692.9 MB/s (11.3%)
 C fill (shuffle within 16 byte blocks)               :  32590.8 MB/s (0.4%)
 C fill (shuffle within 32 byte blocks)               :  32490.2 MB/s (0.3%)
 C fill (shuffle within 64 byte blocks)               :  32638.4 MB/s (0.6%)
 ---
 standard memcpy                                      :  13689.7 MB/s (0.6%)
 standard memset                                      :  32481.3 MB/s (6.6%)
 ---
 NEON LDP/STP copy                                    :  13698.7 MB/s (8.7%)
 NEON LDP/STP copy pldl2strm (32 bytes step)          :  13278.6 MB/s (2.3%)
 NEON LDP/STP copy pldl2strm (64 bytes step)          :  13252.9 MB/s (0.4%)
 NEON LDP/STP copy pldl1keep (32 bytes step)          :  13101.1 MB/s (1.9%)
 NEON LDP/STP copy pldl1keep (64 bytes step)          :  13140.6 MB/s (1.1%)
 NEON LD1/ST1 copy                                    :  13496.3 MB/s (0.4%)
 NEON STP fill                                        :  32511.8 MB/s (5.9%)
 NEON STNP fill                                       :  32770.8 MB/s (8.4%)
 ARM LDP/STP copy                                     :  13682.9 MB/s (0.8%)
 ARM STP fill                                         :  32467.4 MB/s (2.0%)
 ARM STNP fill                                        :  32205.5 MB/s

==========================================================================
== Memory latency test                                                  ==
==                                                                      ==
== Average time is measured for random memory accesses in the buffers   ==
== of different sizes. The larger is the buffer, the more significant   ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM      ==
== accesses. For extremely large buffer sizes we are expecting to see   ==
== page table walk with several requests to SDRAM for almost every      ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest).                                         ==
==                                                                      ==
== Note 1: All the numbers are representing extra time, which needs to  ==
==         be added to L1 cache latency. The cycle timings for L1 cache ==
==         latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
==         two independent memory accesses at a time. In the case if    ==
==         the memory subsystem can't handle multiple outstanding       ==
==         requests, dual random read has the same timings as two       ==
==         single reads performed one after another.                    ==
==========================================================================

block size : single random read / dual random read, [MADV_NOHUGEPAGE]
      1024 :    0.0 ns          /     0.0 ns
      2048 :    0.0 ns          /     0.0 ns
      4096 :    0.0 ns          /     0.0 ns
      8192 :    0.0 ns          /     0.0 ns
     16384 :    0.0 ns          /     0.0 ns
     32768 :    0.0 ns          /     0.0 ns
     65536 :    0.0 ns          /     0.0 ns
    131072 :    0.9 ns          /     1.2 ns
    262144 :    1.7 ns          /     2.2 ns
    524288 :    3.4 ns          /     4.4 ns
   1048576 :    9.1 ns          /    12.3 ns
   2097152 :   12.2 ns          /    15.4 ns
   4194304 :   16.8 ns          /    20.1 ns
   8388608 :   64.3 ns          /    86.5 ns
  16777216 :  100.1 ns          /   129.8 ns
  33554432 :  127.4 ns          /   153.3 ns
  67108864 :  146.2 ns          /   163.5 ns

block size : single random read / dual random read, [MADV_HUGEPAGE]
      1024 :    0.0 ns          /     0.0 ns
      2048 :    0.0 ns          /     0.0 ns
      4096 :    0.0 ns          /     0.0 ns
      8192 :    0.0 ns          /     0.0 ns
     16384 :    0.0 ns          /     0.0 ns
     32768 :    0.0 ns          /     0.0 ns
     65536 :    0.0 ns          /     0.0 ns
    131072 :    0.8 ns          /     1.2 ns
    262144 :    1.6 ns          /     2.0 ns
    524288 :    3.2 ns          /     4.1 ns
   1048576 :    8.9 ns          /    12.3 ns
   2097152 :   12.2 ns          /    15.3 ns
   4194304 :   16.7 ns          /    20.4 ns
   8388608 :   60.4 ns          /    84.4 ns
  16777216 :  101.2 ns          /   130.0 ns
  33554432 :  125.6 ns          /   148.5 ns
  67108864 :  140.5 ns          /   156.2 ns

Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.

tinymembench v0.4.9 (simple benchmark for memory thr

==========================================================================
== Memory bandwidth tests                                               ==
==                                                                      ==
== Note 1: 1MB = 1000000 bytes                                          ==
== Note 2: Results for 'copy' tests show how many bytes can be          ==
==         copied per second (adding together read and writen           ==
==         bytes would have provided twice higher numbers)              ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
==         to first fetch data into it, and only then write it to the   ==
==         destination (source -> L1 cache, L1 cache -> destination)    ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in    ==
==         brackets                                                     ==
==========================================================================

 C copy backwards                                     :   2949.7 MB/s (3.8%)
 C copy backwards (32 byte blocks)                    :   3011.8 MB/s
 C copy backwards (64 byte blocks)                    :   3029.2 MB/s
 C copy                                               :   3642.2 MB/s (4.1%)
 C copy prefetched (32 bytes step)                    :   3824.4 MB/s (0.3%)
 C copy prefetched (64 bytes step)                    :   3825.3 MB/s (0.4%)
 C 2-pass copy                                        :   2726.2 MB/s
 C 2-pass copy prefetched (32 bytes step)             :   2902.6 MB/s (2.5%)
 C 2-pass copy prefetched (64 bytes step)             :   2928.3 MB/s (0.3%)
 C fill                                               :   8541.0 MB/s (0.2%)
 C fill (shuffle within 16 byte blocks)               :   8518.5 MB/s (2.1%)
 C fill (shuffle within 32 byte blocks)               :   8537.1 MB/s (0.1%)
 C fill (shuffle within 64 byte blocks)               :   8528.7 MB/s (0.2%)
 ---
 standard memcpy                                      :   3558.8 MB/s
 standard memset                                      :   8520.2 MB/s
 ---
 NEON LDP/STP copy                                    :   3633.9 MB/s (4.2%)
 NEON LDP/STP copy pldl2strm (32 bytes step)          :   1451.0 MB/s (0.3%)
 NEON LDP/STP copy pldl2strm (64 bytes step)          :   1450.9 MB/s (0.5%)
 NEON LDP/STP copy pldl1keep (32 bytes step)          :   3882.5 MB/s (3.9%)
 NEON LDP/STP copy pldl1keep (64 bytes step)          :   3884.0 MB/s (0.4%)
 NEON LD1/ST1 copy                                    :   3630.8 MB/s (0.3%)
 NEON STP fill                                        :   8537.8 MB/s
 NEON STNP fill                                       :   8544.9 MB/s (1.7%)
 ARM LDP/STP copy                                     :   3635.8 MB/s (0.3%)
 ARM STP fill                                         :   8544.8 MB/s (0.1%)
 ARM STNP fill                                        :   8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests.                                              ==
==                                                                      ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled.       ==
== Writes to such framebuffers are quite fast, but reads are much       ==
== slower and very sensitive to the alignment and the selection of      ==
== CPU instructions which are used for accessing memory.                ==
==                                                                      ==
== Many x86 systems allocate the framebuffer in the GPU memory,         ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover,    ==
== PCI-E is asymmetric and handles reads a lot worse than writes.       ==
==                                                                      ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer    ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall    ==
== performance improvement. For example, the xf86-video-fbturbo DDX     ==
== uses this trick.                                                     ==
==========================================================================

 NEON LDP/STP copy (from framebuffer)                 :    766.0 MB/s
 NEON LDP/STP 2-pass copy (from framebuffer)          :    688.8 MB/s
 NEON LD1/ST1 copy (from framebuffer)                 :    770.6 MB/s (0.1%)
 NEON LD1/ST1 2-pass copy (from framebuffer)          :    681.3 MB/s (0.3%)
 ARM LDP/STP copy (from framebuffer)                  :    766.1 MB/s
 ARM LDP/STP 2-pass copy (from framebuffer)           :    689.1 MB/s


==========================================================================
== Memory latency test                                                  ==
==                                                                      ==
== Average time is measured for random memory accesses in the buffers   ==
== of different sizes. The larger is the buffer, the more significant   ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM      ==
== accesses. For extremely large buffer sizes we are expecting to see   ==
== page table walk with several requests to SDRAM for almost every      ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest).                                         ==
==                                                                      ==
== Note 1: All the numbers are representing extra time, which needs to  ==
==         be added to L1 cache latency. The cycle timings for L1 cache ==
==         latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
==         two independent memory accesses at a time. In the case if    ==
==         the memory subsystem can't handle multiple outstanding       ==
==         requests, dual random read has the same timings as two       ==
==         single reads performed one after another.                    ==
==========================================================================

block size : single random read / dual random read, [MADV_NOHUGEPAGE]
      1024 :    0.0 ns          /     0.1 ns 
      2048 :    0.0 ns          /     0.1 ns 
      4096 :    0.0 ns          /     0.1 ns 
      8192 :    0.0 ns          /     0.1 ns 
     16384 :    0.1 ns          /     0.1 ns 
     32768 :    1.7 ns          /     2.9 ns 
     65536 :    6.4 ns          /     9.5 ns 
    131072 :    9.6 ns          /    12.3 ns 
    262144 :   13.7 ns          /    17.0 ns 
    524288 :   15.8 ns          /    19.7 ns 
   1048576 :   17.3 ns          /    22.1 ns 
   2097152 :   42.1 ns          /    64.2 ns 
   4194304 :   98.5 ns          /   138.1 ns 
   8388608 :  143.9 ns          /   186.3 ns 
  16777216 :  167.2 ns          /   211.2 ns 
  33554432 :  180.1 ns          /   227.1 ns 
  67108864 :  200.0 ns          /   260.2 ns 
block size : single random read / dual random read, [MADV_HUGEPAGE]
      1024 :    0.0 ns          /     0.0 ns 
      2048 :    0.0 ns          /     0.0 ns 
      4096 :    0.0 ns          /     0.0 ns 
      8192 :    0.0 ns          /     0.0 ns 
     16384 :    0.0 ns          /     0.0 ns 
     32768 :    0.0 ns          /     0.0 ns 
     65536 :    6.4 ns          /     9.4 ns 
    131072 :    9.5 ns          /    12.2 ns 
    262144 :   11.2 ns          /    13.1 ns 
    524288 :   12.1 ns          /    13.5 ns 
   1048576 :   12.8 ns          /    13.6 ns 
   2097152 :   27.0 ns          /    33.0 ns 
   4194304 :   90.6 ns          /   127.8 ns 
   8388608 :  123.9 ns          /   153.8 ns 
  16777216 :  139.5 ns          /   161.2 ns 
  33554432 :  147.2 ns          /   163.6 ns 
  67108864 :  154.0 ns          /   167.6 ns 
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